1. Technical Field
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having a vertical transistor, and a method of fabricating the same.
2. Discussion of the Related Art
With an increase in integration density of a semiconductor memory device such as a DRAM device, the area of a memory device formed on a wafer is reduced, and respective areas occupied by a transistor and a capacitor are reduced at a predetermined ratio. An essential component element of the semiconductor memory device is a memory element capable of storing one bit data, that is, a memory cell. The DRAM comprises several cells, each cell composed of one transistor and one capacitor, and a peripheral circuit capable of reading and writing to store data to the cell.
Currently, a transistor of the DRAM device is formed as a planar transistor. When integration density of the semiconductor memory device is increased, a planar area occupied by the transistor of the DRAM device is reduced. Hence, a channel length of the planar transistor is reduced, which results in a short channel effect. As a result, leakage current of the DRAM cell is increased so that refresh characteristics of the DRAM device may be degraded.
A DRAM cell having a vertical transistor capable of increasing integration density of the DRAM device and preventing a short channel effect phenomenon of the transistor is disclosed by H. Takato, et. al. in an article entitled, “Impact of Surrounding Gate Transistor (SGT) for Ultra-high Density LSI's” (IEEE Transactions on Electron Devices, March 1991, pp. 573-577).
In the article, the surrounding gate transistor is disposed vertically from a semiconductor substrate. The surrounding gate transistor is structured such that a semiconductor pillar is disposed protruded from the semiconductor substrate, and source and drain regions are disposed in an upper portion and a lower portion of the semiconductor pillar, respectively. A gate electrode is disposed to surround the semiconductor pillar, and a gate insulating layer is interposed between the gate electrode and the semiconductor pillar. A channel region is disposed vertically inside the semiconductor pillar. The surrounding gate transistor may be called a vertical transistor.
Further, a method of fabricating a DRAM cell having such a vertical transistor is disclosed in U.S. Pat. No. 6,027,975, entitled, “Process for fabricating vertical transistors”.
However, the article and the U.S. Pat. No. 6,027,975 disclose only a vertical transistor (surrounding gate transistor) in a cell region. In order to fabricate a DRAM device using the vertical transistor, several cells, each composed of one transistor and one capacitor, and a peripheral circuit capable of reading and writing data to the cells as described above are prepared. Thus, it is necessary to consider processes for forming elements in a peripheral circuit region.
When a peripheral circuit transistor of the elements of the peripheral circuit region is formed concurrently with a vertical transistor in the cell region, and thus, is formed as a peripheral circuit vertical transistor, processes may be shortened, and production costs can be reduced. However, since the peripheral circuit vertical transistor is degraded in its device characteristics compared to the planar transistor, the peripheral circuit vertical transistor may not provide the performance characteristics as high as required for the device characteristics of a peripheral circuit transistor.
Therefore, it is necessary to form a vertical transistor in the cell region, and to maintain a planar transistor in the peripheral circuit region. In this case, a vertical transistor may be formed in the cell region first, and then a planar transistor may be formed in the peripheral circuit region. The method may have a problem that the number of processes is increased. Therefore, it is required to study the method of shortening the number of processes to form a vertical transistor and a planar transistor in the cell region and the peripheral circuit region, respectively.